The present invention relates generally to shallow trench isolations (STI), and more particularly, to methods of forming an STI in a semiconductor device including a silicon-on-insulator (SOI) and bulk silicon regions.
As technologies become increasingly complex, demand for integrated circuits (IC) customer having more functionality is growing. In order to provide ICs with optimum designs, high-performance complementary metal-oxide semiconductors (CMOS) devices are required with additional features such as enhanced dynamic random access memory (eDRAM) or radio frequency (RF) applications. A challenge that arises relative to providing all of these features is that each feature is optimized under different conditions. For example, high-performance CMOS may be completed on silicon on insulator (SOI) wafers but RF and eDRAM may be built in bulk silicon.
Conventional techniques exist for making patterned SOI (part bulk and part SOI) wafers for the purposes of merging the best of “bulk technologies” with the best of “SOI technologies.” One such technique that utilizes this approach is integrating eDRAM in SOI. In this case, the eDRAM array blocks are built in bulk silicon and logic is built in the SOI. Another technique that may use this approach is the emerging 65 nm on SOI technology. Substrates at the 65 nm stage may be comprised of Nfets on SOI and Pfets in bulk silicon. This process technology is referred to as “HOT” for Hybrid Orientation Technology.
One challenge facing both examples mentioned above is that fabricators must provide isolation of active diffusions for both SOI and bulk regions. Conventional techniques for providing this isolation require two separate shallow trench processes: one for the bulk silicon and one for the SOI. The above-described process is very complicated and cost-ineffective. In particular, there are a number of challenges with shallow trench isolation (STI) processing relative to patterned SOI versus bulk silicon.
A first challenge relates to the depth of etching for the STI. For SOI regions, the depth of the STI etch is the thickness of the silicon and the etch stops on top of the buried insulator, which is usually under 1000A in depth. For bulk processes, however, the depth of the STI is much deeper than current SOI thickness, e.g., usually 3500A or deeper. When patterning the SOI, there are a few choices for selecting an STI etch depth relative to bulk silicon. A first choice is to use the SOI STI etch depth, which does not give enough isolation in the bulk area. A second choice is to use the bulk STI etch depth, which is a very difficult etch to perform in the SOI region. A third choice is to have the STI etch depth in the SOI region equal to the normal depth in the SOI STI process and have the bulk silicon region depth equal to the normal bulk STI depth. This process, however, requires an extra photoresist layer and is likely to cause problems with STI planarization.
A second challenge with STI processing in patterned SOI arises from a particular process defect that is intrinsic to wafers created by using the Separation by Implantation of Oxygen (SIMOX) process. In a patterned SIMOX process, oxide hardmask islands are initially created on a bulk wafer, shielding wafer regions from a high-dose, high-energy oxygen implant. During the formation of the buried oxide (BOX), through a high-temperature oxidation procedure, the edges of the BOX (i.e., the BOX at the SOI-bulk boundary) become thicker than the BOX in the SOI field regions. In many instances along the boundary of the SOI-bulk area, the buried oxide actually breaches the surface of the wafer. Because an oxide etch is needed to remove the oxide that is grown on a SIMOX wafer, those areas where the buried oxide breaches the surface are also etched away leaving small divots on the wafer surface. The wafers then go through pad oxidation and pad silicon nitride (SiN) deposition. In the SiN deposition process, these holes become filled with nitride and can remain on the patterned wafer throughout most of the STI processing if they are not etched during the STI etch process. Once STI has been filled and planarized, pad SiN needs to be stripped off the wafer surface. Divots which form near the surface that have SiN plugged into them become free of SiN after etching, and will remain free of material until the next deposition step, i.e., gate polysilicon. Since polysilicon can be made electrically active either by doping or conversion to silicide divots filled with polysilicon can cause device shorting. This problem has been observed in early SOI eDRAM hardware. Thus, patterned SIMOX wafers must incorporate a process whereby nitride residuals lying in sub-surface divots are removed completely.
In view of the foregoing, there is a need in the art for a process the addresses the problems of the related art.